It’s both lack of competition and the end of Moores law. We’ve effectively reached the end of silicon gate sizes and the tooling complexity required to keep shrinking process nodes and increase transistor density is increasing exponentially, so semiconducters no longer get cheaper… and it’s starting to push these cutting edge nodes outside of economic viability for consumer products. I’m sure TSMC is taking a very healthy profit cut for sure but the absolute magic they have to work to have 2nm work at all is beginning to be too much.
It’s been talked about a lot. Lots of people have predicted it.
It does eventually have to end though. And I think even if this isn’t the end, we’re close to the end. At the very least, we’re close to the point of diminishing returns.
Look at the road to here-- We got to the smallest features the wavelength of light could produce (and people said Moore’s Law was dead), so we used funky multilayer masks to make things smaller and Moore lived on. Then we hit the limits of masking and again people said Moore’s Law was dead, so ASML created a whole new kind of light with a narrower wavelength (EUV) and Moore lived on.
But there is a very hard limit that we won’t work around without a serious rethink of how we build chips- the width of the silicon atom. Today’s chips have pathways that are in many cases well under 100 atoms wide. Companies like ASML and TSMC are pulling out all the stops to make things smaller, but we’re getting close to the limit of what’s possible with the current concepts of chip production (using photolithography to etch transistors onto silicon wafers). Not possible like can we do it, but possible like what the laws of physics will let us do.
That’s going to be an interesting change for the industry, it will mean slower growth in processing power. That won’t be a problem for the desktop market as most people only use a fraction of their CPU’s power. It will mean the end of the ‘more efficient chip every year’ improvement for cell phones and mobile devices though.
There will be of course customers calling for more bigger better, and I think that will be served by more and bigger. Chiplets will become more common, complete with higher TDP. That’ll help squeeze more yield out of an expensive wafer as the discarded parts will contain fewer mm^2. Wouldn’t be surprised to see watercooling become more common in high performance workstations, and I expect we’ll start to see more interest in centralized watercooling in the server markets. The most efficient setup I’ve seen so far basically hangs server mainboards on hooks and dunks them in a pool of non-conductive liquid. That might even lead to a rethink of the typical vertical rack setup to something horizontal.
The number has some connection to transistor density, in the sense that a lower number means generally higher density. However there is not any physical feature on the chip that is actually 3nm in length.
It is marketing and it does have meaningful connection to the litho features, but the connection is not absolute. For example Samsung’s 5nm is noticeably more power hungry than TSMC’s 5nm.
I’m of the opinion that this is why liquid cooling is so important to next gen hw. I think they’re going to start spreading out the chips more and sandwiching them like with the dh200s Nvidia is working on
This is what a lack of competition looks like.
However… Twice the price of 4nm? The gains are fairly marginal from what I gather. I don’t think many will bother.
It’s both lack of competition and the end of Moores law. We’ve effectively reached the end of silicon gate sizes and the tooling complexity required to keep shrinking process nodes and increase transistor density is increasing exponentially, so semiconducters no longer get cheaper… and it’s starting to push these cutting edge nodes outside of economic viability for consumer products. I’m sure TSMC is taking a very healthy profit cut for sure but the absolute magic they have to work to have 2nm work at all is beginning to be too much.
It’s been talked about a lot. Lots of people have predicted it.
It does eventually have to end though. And I think even if this isn’t the end, we’re close to the end. At the very least, we’re close to the point of diminishing returns.
Look at the road to here-- We got to the smallest features the wavelength of light could produce (and people said Moore’s Law was dead), so we used funky multilayer masks to make things smaller and Moore lived on. Then we hit the limits of masking and again people said Moore’s Law was dead, so ASML created a whole new kind of light with a narrower wavelength (EUV) and Moore lived on.
But there is a very hard limit that we won’t work around without a serious rethink of how we build chips- the width of the silicon atom. Today’s chips have pathways that are in many cases well under 100 atoms wide. Companies like ASML and TSMC are pulling out all the stops to make things smaller, but we’re getting close to the limit of what’s possible with the current concepts of chip production (using photolithography to etch transistors onto silicon wafers). Not possible like can we do it, but possible like what the laws of physics will let us do.
That’s going to be an interesting change for the industry, it will mean slower growth in processing power. That won’t be a problem for the desktop market as most people only use a fraction of their CPU’s power. It will mean the end of the ‘more efficient chip every year’ improvement for cell phones and mobile devices though.
There will be of course customers calling for more bigger better, and I think that will be served by more and bigger. Chiplets will become more common, complete with higher TDP. That’ll help squeeze more yield out of an expensive wafer as the discarded parts will contain fewer mm^2. Wouldn’t be surprised to see watercooling become more common in high performance workstations, and I expect we’ll start to see more interest in centralized watercooling in the server markets. The most efficient setup I’ve seen so far basically hangs server mainboards on hooks and dunks them in a pool of non-conductive liquid. That might even lead to a rethink of the typical vertical rack setup to something horizontal.
It’s gonna be an interesting next few years…
I was under the impression that anything under like 10nm was just marketing and doesn’t actually refer to transistor density in any meaningful way?
The number has some connection to transistor density, in the sense that a lower number means generally higher density. However there is not any physical feature on the chip that is actually 3nm in length.
This has been true since the late 90s probably.
It is marketing and it does have meaningful connection to the litho features, but the connection is not absolute. For example Samsung’s 5nm is noticeably more power hungry than TSMC’s 5nm.
I’m of the opinion that this is why liquid cooling is so important to next gen hw. I think they’re going to start spreading out the chips more and sandwiching them like with the dh200s Nvidia is working on