AMD’s chiplet strategy in laptops: balancing innovation and power efficiency. AMD says that chiplet design for mainstream mobile APUs is challenging due to power constraints. The chiplet approach has been instrumental in the success of the Ryzen CPU series. In the domain of laptops, AMD is still evaluating how to approach this idea. During a […]
Yeah it’s basically widely known now that chiplet Ryzens have noticeably higher idle power draw than either monolithic Ryzens or monolithic Intel chips. I am curious how Meteor Lake’s chiplets are going to avoid the idle power penalty.
The interposer means a less power is used per bit moved between tiles compared to the substrate AMD uses, and the CPU and GPU tile can be shut down when not needed. This leaves the SoC tile’s 2 LPe-cores and the memory controllers, I/O, and display drivers active so the system can idle without the power-hungry parts of the chip doing anything. Current monolithic Ryzen and Core i can’t power down to that extent. Video playback for example, can take place on the LPe-cores, so expect long battery life in that scenario.
Current monolithic Ryzen and Core i can’t power down to that extent.
Why not? I get that the LP-e cores are optimized for lower voltage/frequency than generalist cores historically have been, but monolithic chips can use power gating and multiple voltage domains too.
Video playback for example, can take place on the LPe-cores, so expect long battery life in that scenario.
But what about video playback in a web browser? With 30+ background tabs?
If Meteor Lake manages to avoid regressing real-world battery life, I will be pleasantly surprised.
On current CPUs, anything that needs CPU attention has to wake up the big cores. Ryzen only has big cores currently (Zen4C should be equal power within the frequency both cores can reach) and 12/13th gen Thread Director goes to the P-cores first. This means that every time you need to do something, there is a brief period where some power-hungry cores have to come out of whatever low-power state they use to perform that thing.
With MTL the main CPU tile can in theory stay powered-down while the LPe-cores run code outside of them. Thread Director goes to these cores first, so only tasks that need more CPU are escalated to the main CPU cores.
That is a question I can’t answer right now. It’s a wait and see both because MTL isn’t out yet, and because there are a ton of variables that can change CPU behavior in 30 tabs. Since the memory controllers are on the SoC tile, in theory they can all stay loaded, and only switching between tas would briefly hit the main CPU tile. It is also totally possible that some of those tabs are more demanding, say they leverage some hardware acceleration features of the GPU. That would involve waking that tile during interactions with the page at least.
It’s possible power plans may affect how aggressively tiles are put to sleep, in which case you could get into OEM or even model-specific behaviors that would only be comparable through reviews.
Yeah it’s basically widely known now that chiplet Ryzens have noticeably higher idle power draw than either monolithic Ryzens or monolithic Intel chips. I am curious how Meteor Lake’s chiplets are going to avoid the idle power penalty.
The interposer means a less power is used per bit moved between tiles compared to the substrate AMD uses, and the CPU and GPU tile can be shut down when not needed. This leaves the SoC tile’s 2 LPe-cores and the memory controllers, I/O, and display drivers active so the system can idle without the power-hungry parts of the chip doing anything. Current monolithic Ryzen and Core i can’t power down to that extent. Video playback for example, can take place on the LPe-cores, so expect long battery life in that scenario.
Why not? I get that the LP-e cores are optimized for lower voltage/frequency than generalist cores historically have been, but monolithic chips can use power gating and multiple voltage domains too.
But what about video playback in a web browser? With 30+ background tabs?
If Meteor Lake manages to avoid regressing real-world battery life, I will be pleasantly surprised.
On current CPUs, anything that needs CPU attention has to wake up the big cores. Ryzen only has big cores currently (Zen4C should be equal power within the frequency both cores can reach) and 12/13th gen Thread Director goes to the P-cores first. This means that every time you need to do something, there is a brief period where some power-hungry cores have to come out of whatever low-power state they use to perform that thing.
With MTL the main CPU tile can in theory stay powered-down while the LPe-cores run code outside of them. Thread Director goes to these cores first, so only tasks that need more CPU are escalated to the main CPU cores.
That is a question I can’t answer right now. It’s a wait and see both because MTL isn’t out yet, and because there are a ton of variables that can change CPU behavior in 30 tabs. Since the memory controllers are on the SoC tile, in theory they can all stay loaded, and only switching between tas would briefly hit the main CPU tile. It is also totally possible that some of those tabs are more demanding, say they leverage some hardware acceleration features of the GPU. That would involve waking that tile during interactions with the page at least.
It’s possible power plans may affect how aggressively tiles are put to sleep, in which case you could get into OEM or even model-specific behaviors that would only be comparable through reviews.