There’s been a gradual shifting away from really old designs on equally old and/or ‘hardened’ process nodes, simply due to the age, cost, and performance gap. Also older chips didn’t have the redundancy, self-correcting, and failover capabilities of modern processors, so some of the perceived risk from using much more modern nodes and chip designs is being offset by the redundancy modern chips can provide.
The ESA had been using a series of SPARCv8 cores designed specifically for aerospace applications (with all the associated fault-tolerance, formal verification, and radiation hardening), the LEON series, since the early 1990s. That was back when SPARCv8 was new (it was introduced in the late 1980s). The LEON series has since dropped SPARCv8 (like maybe five years ago), and adopted RISC-V instead (because SPARC is dead, and its ecosystem is dead), so it doesn’t seem to me that NASA is doing anything particularly radical in adopting RISC-V.
I find this odd. Are SiFive RISC-V CPU cores that old already?
There’s been a gradual shifting away from really old designs on equally old and/or ‘hardened’ process nodes, simply due to the age, cost, and performance gap. Also older chips didn’t have the redundancy, self-correcting, and failover capabilities of modern processors, so some of the perceived risk from using much more modern nodes and chip designs is being offset by the redundancy modern chips can provide.
The ESA had been using a series of SPARCv8 cores designed specifically for aerospace applications (with all the associated fault-tolerance, formal verification, and radiation hardening), the LEON series, since the early 1990s. That was back when SPARCv8 was new (it was introduced in the late 1980s). The LEON series has since dropped SPARCv8 (like maybe five years ago), and adopted RISC-V instead (because SPARC is dead, and its ecosystem is dead), so it doesn’t seem to me that NASA is doing anything particularly radical in adopting RISC-V.