Back when Intel introduced the 22nm Tri-Gate process, the great expectations were dashed because the transistor performance gains only materialized at the low clock/low voltage(Atom/GPU) end, while desktops got a regression.

https://www.anandtech.com/show/5771/the-intel-ivy-bridge-core-i7-3770k-review

Intel rejigged the 14nm process after the struggle with first iteration in Broadwell and in Skylake it finally exceeded the clocks on 32nm. Scientists working on processes dream of a process with very, very steep V/F curve.

Intel really ramped up clock focus to the maximum with the 10nm process. Lots of struggles for sure, but the Intel 7 variant shows that the V/F curve is not steep - it benefits high clocked desktop CPUs at the expense of lower power chips. This is part of why Raptorlake mobile catches up and pulls ahead at higher power compared to AMD’s Phoenix, when it loses significantly at lower power envelopes.

With Intel 4 and future variants the V/F curve will be more in line with what TSMC has. This will result in loss of max clocks, but you get better chips that clock lower which will benefit mobile and servers.

Arrowlake

While the Lion Cove cores in Arrowlake are said to be a significant jump with 8-wide decode and over 700 OoOE Reorder buffers, the leaked slides only show a small improvement in ST and modest one in MT.

This can be easily explained. Lion Cove P cores are probably 30% faster than the predecessor Raptor Cove but with significantly reduced clocks. The 30% per/clock gain will turn into ~10% ST gain. That means a roughly 5.5GHz MT clock will go down to 4.6GHz as an example. The reduced clocks are a match with post-Intel 4 changes and to better focus on power efficiency.

The improvements on MT is better because it looks like Skymont is yet another substantial improvement over Crestmont in Meteorlake but with no clock regression. So MT gains are mostly due to the E cores.

Interestingly, this will have a positive side effect in that having the E core on will reduce cases where there is a performance loss, because the gap between the P and the E will be much smaller. The E cores catch up in IPC slightly to the P while the clock gap essentially disappears. Think of a 60% difference being reduced to 30%. The ring will also be able to run at same frequency as the max speed of the cores too. While Raptorlake ring basically has no frequency penalty with E cores on, it’s still not as high clocked as the P cores.

Desktop vs Mobile

Arrowlake has at least two variants. Laptop and Desktop.

Desktop: Likely no LP E cores so it has latest instructions. Some chance of lower end SKUs being basically Meteorlake on an updated process. TSMC N3.

Laptop: LP E cores on the same SoC tile as Meteorlake, which means it will miss some instructions, since LP E cores are Crestmont. Intel 20A process. The HX series are identical to desktop. H is 20A. U is probably all Lunar Lake anyway.

  • III-V@alien.topB
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    1 year ago

    That means a roughly 5.5GHz MT clock will go down to 4.6GHz as an example

    There’s no chance that the drop will be that severe. It will be around 10%

    • Geddagod@alien.topB
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      1 year ago

      If the arch changes are significant, and they try something new- it could easily be much worse than 10% IMO. It’s not like there isn’t precedent for large frequency drops on new Intel products.

  • dmaare@alien.topB
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    1 year ago

    Arrow lake will be very bad if all the leaks about it having disabled HT and only ~5 ST boost over raptor lake come true.

    Most software already expects to use HT nowadays because it’s a standard. Without HT it will likely push stuff on e-waste core which will create latency spikes.

  • Dozck@alien.topB
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    1 year ago

    Is 15th gen Arrowlake? What happened to Meteor Lake that hasn’t come out yet?

    • dmaare@alien.topB
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      1 year ago

      Meteor lake will be performance regression compared to 13th gen H chips so they will only keep meteor lake generation for the low power stuff alongside laptop versions of raptor refresh.

  • Good_Season_1723@alien.topB
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    1 year ago

    If / when Intel reaches node parity and stacked cache, it’s going to send AMD back to the stone age again.

    • Geddagod@alien.topB
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      1 year ago

      Intel’s design teams are worse than AMD’s. That’s not just me saying it, Pat all but said it himself in a recent interview as well. They lost leadership in many key areas, not just what node they use.

  • OfficialHavik@alien.topB
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    1 year ago

    Great analysis!!! My only comment is I damn near guarantee they won’t actually call it 15th gen after the naming/branding changes coming with Meteor Lake.

  • basil_elton@alien.topB
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    1 year ago

    I don’t expect a 30% perf/clock improvement over Raptor Cove cores. I will stick with Intel’s record of delivering ~19% perf/clock with each “tock” in recent years, if we are to still follow that terminology.

    Meteor Lake is targeting 5.0-5.1 GHz fmax on mobile, which is due to how Intel 4 ended up. Historically speaking, in the FinFET era, Intel has a learning phase with process nodes - they take their time to figure out a particular node, address its shortcomings, and then come out hitting hard on the next node shrink.

    It happened with 22nm to 14nm, and again with 10nm (which was a colossal disaster), from which they salvaged Intel 7, where fmax can reach 6 GHz and more!

    Intel 4 is not the disaster that 10nm was, which bodes well for Intel 3. That, coupled with some leaks suggesting that Arrow Lake-S will have a PL2 of 177 W means that Intel 3 is likely to have a steep voltage-frequency curve, therefore I agree with the larger point that you are making.

  • ibmthink@alien.topB
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    1 year ago

    U is probably all Lunar Lake anyway

    Unlikely. Lunar Lake is probably only a limited release for premium ultrabooks. Arrow Lake is the mainstream platform that will power most laptops.

  • jrherita@alien.topB
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    1 year ago

    Variable: Pat Gelsinger referrer to Arrow Lake as a small die. Certainly some of that is due to the tile architecture but Intel could also have shortened the pipeline which would reduce clocks outside of the process/ transistor changes (while also improving latency).

    Good analysis though. We probably won’t see higher clocks until later versions.