• carl2187@alien.topB
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    1 year ago

    Basically the same thing amd is doing with their crazy high L3 cache cpus like the 5800x3d. Sounds like a good idea to apply the idea to GPU’s too.

  • hackenclaw@alien.topB
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    1 year ago

    ELI5,

    why the cache/memory always seems to be on top of the processing chip, not bottom?

    • Nicholas-Steel@alien.topB
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      1 year ago

      Because power delivery throughout a CPU has been from top to bottom for decades (no idea why they went with this in the first place), Intel is working on inverting this and having power delivered from bottom to top and will see this realized in either their Arrowlake or later generation of Desktop CPU’s.

      Potentially this inversion of power delivery will enable them to place the memory beneath everything and improve thermal characteristics.

      • RemarkablePumpk1n@alien.topB
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        1 year ago

        Given everything has been evolution from discrete valve tubes onwards, so there is a lot of it just being the easiest way to provide the connection to the rest of the system in a manner that you can hand off easily to the motherboard designers to be cheaply and efficiently mounted.

      • Exist50@alien.topB
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        1 year ago

        These are all in flip-chip packages. So no, power would come up through the bottom, and the transistors would be closest to the top.

    • monocasa@alien.topB
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      1 year ago

      Heat. The processor generates most of the heat, so you want the back side of the die somewhere a heat spreader can more or less directly connect to.

    • GomaEspumaRegional@alien.topB
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      1 year ago

      Well Top/Bottom is relative. But I assume you meant Top as in the side facing the heatsink.

      Memory is “cooler” than dynamic logic, you want the colder element on top of the hotter one on the path of maximum dissipation.

  • Tom_Robson_@alien.topB
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    1 year ago

    this could be a game changer if they can overcome the cooling and clock speed challenges, but the potential cost savings and production efficiency could make it worth it. excited to see where this goes!

  • ALEKSDRAVEN@alien.topB
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    1 year ago

    I think that wouldnt be cheap solution. Also the idea pehind scraped RDNA 4C and upcoming RDNA5 already show similar solution. Some leaks sugest the same for Zen 6.

  • gburdell@alien.topB
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    1 year ago

    Didn’t Intel’s CEO recently mention putting cache on top of compute was an aspiration of his? Seems to hint that they’re making this

    • Put_It_All_On_Blck@alien.topB
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      1 year ago

      He’s made that statement a few times this year, even like a few weeks ago. Clearly a product is coming, we just dont know when or what.

    • Exist50@alien.topB
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      1 year ago

      No, Intel hasn’t talked about stacking HBM (or similar DRAM tech). They seem to be basically 3-4 years behind TSMC in hybrid bonding.

  • Round0Mma@alien.topB
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    1 year ago

    cool concept but i’m worried about the potential cooling challenges and manufacturing complexities. could be a game changer if they can overcome those hurdles though

  • Tom_Robson_@alien.topB
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    1 year ago

    this could be a game changer if they can overcome the cooling and clock speed challenges, but the potential cost savings and production efficiency could make it worth it. excited to see where this goes!