This is just a nitpicking question. Do Intel chips still have some space/transistors dedicated to SSE3? If they do, why can’t they implement SSE3 by other, more powerful instrutions (like AVX) to save die space?
This is just a nitpicking question. Do Intel chips still have some space/transistors dedicated to SSE3? If they do, why can’t they implement SSE3 by other, more powerful instrutions (like AVX) to save die space?
The x86 instructions go through a translation layer that turns them into CPU specific instructions (microcode). So the CPU doesn’t need any specific hardware to be compatible with these old instructions, it just needs to know how to get the same result with microcode.
You are confusing microcode and micro-ops.
what is microcode is, then?
It’s a way of creating a sequential control circuit based on a piece of memory holding the outputs and next state for each state.
This is incorrect. Very few x86 instructions uses microcode as the microcode engine is quite slow. It’s mainly used for things like
cpuidand such.Microcode is used very heavily in modern CPUs. It has been since the 90s.
A lot of x86 ISA is in the micro and PAL codes. Only the most frequent and performance-limiting ones are on-core for modern x86.
x86 is a huge set, so “very few” is a relative term ;-)
Are there performance losses or gains through this translation?