LBXZero@alien.topBtoAMD@hardware.watch•Speculation on RDNA 4 flagship GPU size and performance and possible release dateEnglish
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1 year agoOne of the fun benefits of the Navi31 die, AMD just needs to adapt the Navi31 main die to the newer fabrication node plus minor updates and polish. The I/O dies hold the memory controllers, so adapting to GDDR7 is just redesigning the I/O dies. If the RDNA4 I/O dies support GDDR7 and are compatible with Navi31, making the Navi31 refresh support GDDR7 won’t require too much effort.
It depends on where bottlenecks lie. Commonly, VRAM bandwidth is such a major bottleneck that graphics engines are designed and tuned to take advantage of the excess GPU power over the VRAM bandwidth limits. For an object in VRAM to be rendered, it must occupy VRAM bandwidth per frame. All the extra VRAM capacity that many tout just allows bigger levels to be stored in VRAM without the need for memory management. If you want higher detail objects in VRAM and rendering them as well, you need bandwidth to accompany the capacity.
Given ray tracing typically increases VRAM memory usage by a substantial amount, it is a wonder, and worthy experiment to see how much VRAM bandwidth is the bottleneck for such performance.