koulib to Linux@lemmy.mlEnglish · 2 days agoWhich new Protocol or Standard are you most excited about?message-squaremessage-square46fedilinkarrow-up183arrow-down13file-text
arrow-up180arrow-down1message-squareWhich new Protocol or Standard are you most excited about?koulib to Linux@lemmy.mlEnglish · 2 days agomessage-square46fedilinkfile-text
minus-squarepizzaboi@lemm.eelinkfedilinkEnglisharrow-up21·2 days agoIs there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
minus-squaredeur@feddit.nllinkfedilinkarrow-up19·edit-22 days agoIn principle it’s just “slimmer ARM”. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports. Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
minus-squaremvirts@lemmy.worldlinkfedilinkarrow-up4·2 days agoI for one think we need a register for each unsigned integer, why is zero so special? :P Or if we can’t get that, at least every power of 2 and power of 2 minus 1. Maybe I can submit a proposal for risc-VI 🤣
minus-squarePetteriPano@lemmy.worldlinkfedilinkarrow-up7·1 day ago Maybe I can submit a proposal for risc-VI 🤣 No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
minus-squareporl@lemmy.worldlinkfedilinkEnglisharrow-up4·1 day agoI think a register for each of the primes should be enough.
minus-squarecaseyweederman@lemmy.calinkfedilinkarrow-up2·2 days agoARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
minus-squareMonkderVierte@lemmy.mllinkfedilinkarrow-up2·1 day agoAren’t they more like a hybrid instruction set and architecture?
Is there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
In principle it’s just “slimmer ARM”. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports.
Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
I for one think we need a register for each unsigned integer, why is zero so special? :P
Or if we can’t get that, at least every power of 2 and power of 2 minus 1.
Maybe I can submit a proposal for risc-VI 🤣
No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
I think a register for each of the primes should be enough.
ARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
Aren’t they more like a hybrid instruction set and architecture?