• 0 Posts
  • 8 Comments
Joined 1 year ago
cake
Cake day: October 19th, 2023

help-circle





  • It’s more likely MS didn’t think taking a whole bunch Geona systems out of use elsewhere would be worth it. The backlog for Genoa throughout most of h1 made them nearly as unobtainable as H100s.

    Most of the CPU time in these sort of systems is usually taken up by relatively basic PCIe traffic management. More likely, SPR and Geona are basically interchangeable as far as this is concerned and SPR Xeon just had less opportunity cost.

    If there was actually any special sauce that made a tangible difference with this type of setup, there would be an epic bumrush by everyone to buy up SPR Xeons to host all their H100s, but they’re clearly not. Nvidia would have also made a far bigger and more public stink over Intel’s failure to deliver SPR on time, due to DGX-H100.



  • That’s only explicitly true for Intel.

    The manufacturing method for Ryzen chiplet & Epyc are basically identical, with a different IOD and packaging complexity being the only real differences, so any additional production costs predominantly down to that part instead of something related to the wafer.

    Yield/binning costs cancels themselves out because a CCD, the single most expensive part to design and manufacture, has all of its costs spread across the entire Epyc & Ryzen chiplet product stack. Intel doesn’t have that luxury, since Xeon & Core-S are two different sets of designs.

    Ryzen APUs are a fundamentally different design to all the other Ryzen/Epyc stack. So even if the mobile chips command a higher ASP than Ryzen chiplet, they also carry with them a higher manufacturing cost because it isn’t subsidised by being part of the CCD production line.