They need to beat 4070 at the beginning of the cycle. Or at least 4070 Ti level mid-cycle. And that’s just old x070 non-Ti level performance to begin with.
They need to beat 4070 at the beginning of the cycle. Or at least 4070 Ti level mid-cycle. And that’s just old x070 non-Ti level performance to begin with.
This is not true. Here’s Intel’s official slide on it
This is not true. Here’s Intel’s official slide on it.
Your slide is Xe, not Xe-LP
Why would they bother to REMOVE GeForce branding? They are designed and manufactured with it.
Are you stupid? You sure think everyone else is.
These are AI solutions, how stupid can you be if you’d think they are genuine cards? IN CHINA, where it’s banned.
told Satya that they want be the TSMC of AI.
That’s just a pipedream. They are peacocking and it’s obviously failing since Microsoft shat directly in their face with Maia.
Nvidia’s ecosystem advantages will only diminish over the years since Microsoft, Google and Amazon etc will develop their own.
This is Glide vs Direct3D all over again. You know which one won.
No. Tensor cores have seperate specialised matrix ALUs, AMD’s WMMA are instructions on existing shader ALUs.
Tensor cores can process AI tasks in parallel to CUDA cores, RDNA3 can’t do both on the same CU.
It is also no big secret that the Chinese government exercises a fair amount of control over the companies that operate within its borders, and that the CCP takes particular issue over Taiwanese independence.
Put on your tinfoil hat and stay in your mom’s basement. What a stupid comment!
Is this why blackholes exist too? Can CCP throw you into one? You are obviously the publicly enemy number 10384937, CCP must hate you to guts.
the antitrust lawsuit that broke up Microsoft in the 90s
You have entered the wrong timeline. Go back to where you came from
Software stack is completely useless for datacenters. Nobody is using off-the-shelf solutions.
Google, Amazon, Microsoft are all building custom chips, you think they need AMD software stack if they bought MI300?
All they need is close-to-metal access via minimal driver.
Only the physical design. Also there’s no such requirement, not that strict anyways. Much smaller companies have worked with both, e.g. Tenstorrent. AMD can easily manage that.
Because every design flaw from Apple is a Feature-not-a-Bug™, costs a fortune to fix and they don’t fix it for free without immense publicity pressure.
Even then, it’s a goodwill, they did nothing wrong.
Technically yes
Techunically IMPOSSIBLE. Not on any existing APU chips or Zen4c chiplet. There’s no TSV contacts to connect the cache.
It’ll require a complete redesign of the chip. But it’s possible if AMD did that.
but AMD had used monolithic dies for their APUs
Irrelevant.
add cache on top of a bigger piece of silicon than a CPU chiplet would need a redesign at least
No. Size is completely irrelevant. Redesign is needed indeed, but it’s the APU that needed redesign, not the cache.
and it would jack up prices quite significantly
No. The filler silicon ALSO USED ON CURRENT X3D costs a few cents at most. Even 200mm² costs pennies.
reducing prices
Funny how increasing supply chain cost will reduce price.
For comparison, AMD’s 7950X gets 84.06 ns using 4 KB pages over a 1 GB array. AMD’s Phoenix suffers from higher latency and hits 126.7 ns with the same 1 GB test size.
It’s a bit annoying when he wrote “for comparison” but these are of UNKOWN quality. 84.06ns on what memory configuration? Suffers from 126.7ns on what configuration?
Previously graph shows bandwidth of less than 100GB/s, and it looks like 85-90GB/s. It could be LPDDR5-5500 or DDR5-5600 of various timings. Again no mention if these are even on the same system. 126ns sounds like JEDEC DDR5-5600B. So if the desktop is using something like DDR5-6000 CL36 then that latency really has nothing to do with Phoenix.
Completely false. 2.4b transistors would mean it’s less than 1/3 as dense on the same node while being lower performant (so HP cells are not a factor). Why on earth would you even use 7nm when 20nm (and even 28nm) can reach that density easily.
Use you brain. Just because TPU listed wrong data, doesn’t mean you have to parrot it.
It has 40% the CU, 50% the CPU, 80% memory bus, nearly 100% front end (geometry, ACE etc), 100% display, video, I/O etc.
At bare minimum you are looking at 70% transistor count.