The bandwidth issues of these APUs can be solved with large on-die cache. But the problem with SRAM is that it takes up a lot of die space. And with CPU + GPU already on the die, there isn’t much space left for the cache.
However, this problem can be solved with chiplets. Though I’m not sure if there’s a market for ‘high-end’ APUs!
Can’t say I fully grasp the concept, but it seems like these ‘transistors’ are a replacement for traditional TIM and solder?
You just put a layer of them between the die and IHS and… magic happens?!
Sounds like a great way to cool-down 3D stacked dies.
A quad-core or - at most - an octa-core cluster of E-Cores should be more than enough for handling ‘mundane’ background activity while the P-Cores are busy doing all the heavy-lifting.
They’re to maximize MT performance in a given die space.
And I never said otherwise.
I explicitly mentioned that more E-Cores can boost scores in multi-threaded synthetic benchmark and - in turn - any parallel workload.
Well, applications are definitely getting optimized for 8C/16T as of late so it won’t be all that surprising.
Hyper-threaded threads (hyper-threads?) can’t match an actual core by design, after all.
However, I’m merely question the addition of 8+ E-Cores in Intel’s high-end SKUs. I believe I explicitly mentioned that I can see the potential of integrating 4 to 8 E-Cores into a CPU.
From what I’m seeing, even with APO enabled, only 4 E-Cores are actually doing anything. The rest of the cluster is parked, doing absolutely nothing.
Actually, that’s false. They’re actually consuming power, how miniscule it may be!
And that’s one of the many reasons I don’t understand why Intel is stuffing so many E-Cores into their CPUs. Their practicality in real-world scenarios is mostly academic from the perspective of most users.
A quad-core or - at most - an octa-core cluster of E-Cores should be more than enough for handling ‘mundane’ background activity while the P-Cores are busy doing all the heavy-lifting.
Frankly, I just can’t help but feel like the purpose of these plethora of little cores it to artificially boost scores in multi-core synthetic benchmarks! After all, there are only a handful of ‘consumer-grade’ programs which are parallel enough to actually make use of a CPU with 32 threads.
Anyhow, fingers crossed for Intel’s mythical ‘Royal Core.’ A tile-based CPU architecture sans hyper-threading sounds pretty interesting… at least on paper.
I’ve no idea why all of a sudden everyone’s concerned about idle power consumption!
Anyhow, it’s just a myth that Zen4 has high idle power draw than Raptor Lake. Per Guru3D, the Ryzen 9 7950X3D has a total system idle of 78W, compared to i9-13900K’s 69W. That’s only 13%.
And in single and multli-threaded application, the 7950X3D draws 114W and 264W, respectively, compared to 13900K’s 124W and a whopping 368W.
And let’s not forget that the 7950X3D is a chiplet based CPU with high-bandwidth interconnects and a massive 32+96MB 3D V-Cache on-board. The fact that it’s only marginally more power hungry than the monolithic 13900K at idle is quite an achievement.
So… SMIC is on par with Intel?!
/s
Anyhow, this article is clearly politically motivated so I’m not going to fall for this trap.
But let’s assume that SMIC 7nm is on par with TSMC N7, that means China is just 2 full-nodes behind (N5, N3), not 5.
With 5 nodes, we are talking about TSMC 16nm and Samsung 14nm!
Well, for one thing, you just proved my point! Clearly, chips fabbed on Intel 7 have far higher leakage than TSMC N6, hence they require more voltage at any given frequency to stay stable.
Secondly, voltage is just one side of the equation. You also have to consider current because of Ohm’s Law. For example, an RTX4090 running at 1V will have far higher power consumption than an RTX4060, also running at 1V.
And, clearly, Intel is injecting far more current into their chips than AMD which not only translates into high power consumption and heat (more amps = more heat) but also compromises long-term longevity of the silicon die.
Pushing silicon chips way past their optimum voltage/frequency curve, just to match the performance of 2X more power efficient competition, is hardly “progress.” Same goes to brand renames.
It’s Phenom I vs. Core 2 Quad all over again, only the roles have been reversed!
For example, AMD’s 2.5GHz Phenom I X4 9850 required 125W. Less than 6 months later, Intel released the 2.8GHz Core 2 Quad Q9550S which ran at 65W and had superior IPC to boot.
And then there was the Sandy Bridge, released just 2 years later, which could easily break the 4GHz barrier with stock voltages and cooler.
Intel - or rather their foundry - really need to step-up their game. Otherwise, Zen5 - with its rumored ~20-30% IPC uplift - is going to make things very difficult for Intel.
For perspective, Sandy Bridge had 20% and 25% superior IPC to Nehalem and Core, respectively.
Yet these chiplets still run much cooler than the monolithic dies the ‘competition’ has been churning out as of late!
Dimensity 7020 a.k.a 930 has a dual-core cluster of A78s paired with a hexa-core cluster of A55s.
That’s plenty of horsepower, though day-to-day performance mostly depends on the storage, as opposed to RAM or CPU.
For example, my smartphone has a Snapdragon 680 paired with UFS 2.2 storage and it comfortable outpaces smartphones with faster CPUs albeit (much) slower eMMC memory.
This comparison video ought to give you an idea:
https://www.youtube.com/watch?v=f7KNkvyEUWA&pp=ygULZW1tYyB2cyB1ZnM%3D